EP2C20F256C8N Datasheet, PDF (378/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

PS Configuration
Configuration Stage
After the Cyclone II device’s nSTATUS pin transitions high, the MAX II
device should send the configuration data on the DATA0 pin one bit at a
time. If you are using configuration data in RBF, HEX, or TTF format,
send the least significant bit (LSB) of each data byte first. For example, if
the RBF contains the byte sequence 02 1B EE 01 FA, you should transmit
the serial bitstream 0100-0000 1101-1000 0111-0111 1000-0000
0101-1111 to the device first.
The Cyclone II device receives configuration data on its DATA0 pin and
the clock on the DCLK pin. Data is latched into the FPGA on the rising
edge of DCLK. Data is continuously clocked into the target device until the
CONF_DONE pin transitions high. After the Cyclone II device receives all
the configuration data successfully, it releases the open-drain
CONF_DONE pin, which is pulled high by an external 10-kΩ pull-up
resistor. A low-to-high transition on CONF_DONE indicates configuration
is complete and initialization of the device can begin. The CONF_DONE
pin must have an external 10-kΩ pull-up resistor in order for the device
to initialize.
The configuration clock (DCLK) speed must be below the specified system
frequency (see Table 13–7) to ensure correct configuration. No maximum
DCLK period exists, which means you can pause configuration by halting
DCLK for an indefinite amount of time.
Initialization Stage
In Cyclone II devices, the initialization clock source is either the
Cyclone II internal oscillator (typically 10 MHz) or the optional CLKUSR
pin. The internal oscillator is the default clock source for initialization. If
you use the internal oscillator, the Cyclone II device makes sure to
provide enough clock cycles for proper initialization. Therefore, if the
internal oscillator is the initialization clock source, sending the entire
configuration file to the device is sufficient to configure and initialize the
device. You do not need to provide additional clock cycles externally
during the initialization stage. Driving DCLK back to the device after
configuration is complete does not affect device operation. Additionally,
if you use the internal oscillator as the clock source, you can use the
CLKUSR pin as a user I/O pin.
If you want to delay the initialization of the device, you can use the
CLKUSR pin. Using the CLKUSR pin allows you to control when your
device enters user mode. You can delay the device from entering user
mode for an indefinite amount of time.
13–24
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007