EP2C20F256C8N Datasheet, PDF (320/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Referenced Documents
Referenced
Documents
This chapter references the following documents:
■ Altera Reliability Report
■ AN 75: High-Speed Board Designs
■ Cyclone II Architecture chapter in volume 1 of the Cyclone II Device
Handbook
■ Cyclone II Device Family Data Sheet, section 1 of the Cyclone II Device
Handbook
■ DC Characteristics and Timing Specifications chapter in volume 1 of the
Cyclone II Device Handbook
■ External Memory Interfaces chapter in volume 1 of the Cyclone II Device
Handbook
■ High Speed Differential Interfaces in Cyclone II Devices chapter in
volume 1 of the Cyclone II Device Handbook
■ Hot Socketing & Power-On Reset chapter in volume 1 of the Cyclone II
Device Handbook
■ I/O Management chapter in volume 2 of the Quartus II Handbook
Document
Table 10–13 shows the revision history for this document.
Revision History
Table 10–13. Document Revision History
Date and
Document
Version
February 2008
v2.4
February 2007
v2.3
Changes Made
Summary of Changes
● Added “Referenced Documents” section.
—
● Updated “Differential Pad Placement
Guidelines” section.
● Added document revision history.
● Updated “Introduction” and its feetpara
note.
● Updated Note (2) in Table 10–4.
● Updated “Differential LVPECL” section.
● Updated “Differential Pad Placement
Guidelines” section.
● Updated “Output Pads” section.
● Added new section “5.0-V Device
Compatibility” with two new figures.
● Added reference detail for ESD
specifications.
● Added information about differential
placement restrictions applying only to pins
in the same bank.
● Added information that Cyclone II device
supports LVDS on clock inputs at 3.3V
V_CCIO.
● Added more information on DC placement
guidelines.
● Added information stating SSTL and HSTL
outputs can be closer than 2 pads from
V_REF..
● Added 5.0 Device tolerence solution.
10–38
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008