EP2C20F256C8N Datasheet, PDF (199/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

PLLs in Cyclone II Devices
Each output port has a unique post-scale counter to divide down the
high-frequency VCO. There are three post-scale counters (c0, c1, and c2),
which range from 1 to 32. The following equations show the frequencies
for the three post-scale counters:
f_C0 =
f_VCO
C0
= f_IN
m
n × C0
f_C1 =
f_VCO
C1
= f_IN
m
n × C1
f_C2 =
f_VCO
C2
= f_IN
m
n × C2
All three output counters can drive the global clock network. The c2
output counter can also drive a dedicated external I/O pin (single ended
or differential). This counter output can drive a dedicated external clock
output pin (PLL<#>_OUT) and the global clock network at the same time.
For multiple PLL outputs with different frequencies, the VCO is set to the
least common multiple of the output frequencies that meets the VCO
frequency specifications. Then, the post-scale counters scale down the
VCO frequency for each PLL clock output port. For example, if clock
output frequencies required from one PLL are 33 and 66 MHz, the VCO
is set to 330 MHz (the least common multiple in the VCO’s range).
Programmable Duty Cycle
The programmable duty cycle feature allows you to set the PLL clock
output duty cycles. The duty cycle is the ratio of the clock output high and
low time to the total clock cycle time, expressed as a percentage of high
time. This feature is supported on all three PLL post-scale counters, c0, c1,
and c2, and when using all clock feedback modes.
The duty cycle is set by using a low- and high-time count setting for the
post-scale counters. The Quartus II software uses the input frequency and
target multiply/divide ratio to select the post-scale counter. The
granularity of the duty cycle is determined by the post-scale counter
value chosen on a PLL clock output and is defined as 50% ÷ post-scale
counter value. For example, if the post-scale counter value is 3, then the
allowable duty cycle precision would be 50% ÷ 3 = 16.67%. Because the
altpll megafunction does not accept non-integer values for the duty
cycle values, the allowable duty cycles are 17% 33% 50% and 67%. For
example, if the c0 counter is 10, then steps of 5% are possible for duty
cycle choices between 5 to 90%.
Altera Corporation
February 2007
7–15
Cyclone II Device Handbook, Volume 1