EP2C20F256C8N Datasheet, PDF (67/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II Architecture
The pin’s datain signals can drive the logic array. The logic array drives
the control and data signals, providing a flexible routing resource. The
row or column IOE clocks, io_clk[5..0], provide a dedicated routing
resource for low-skew, high-speed clocks. The global clock network
generates the IOE clocks that feed the row or column I/O regions (see
“Global Clock Network & Phase-Locked Loops” on page 2–16).
Figure 2–23 illustrates the signal paths through the I/O block.
Figure 2–23. Signal Path Through the I/O Block
Row or Column
io_clk[5..0]
To Other
IOEs
To Logic
Array
io_datain0
io_datain1
oe
io_csclr
ce_in
io_coe
ce_out
Data and
aclr/preset
IOE
io_cce_in
Control
From Logic
io_cce_out
Signal
Selection
sclr/preset
Array
clk_in
io_caclr
io_cclk
clk_out
io_dataout
dataout
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset,
clk_in, and clk_out. Figure 2–24 illustrates the control signal
selection.
Altera Corporation
February 2007
2–41
Cyclone II Device Handbook, Volume 1