EP2C20F256C8N Datasheet, PDF (169/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

DC Characteristics and Timing Specifications
Table 5–53 shows the JTAG timing parameters and values for Cyclone II
devices.
Table 5–53. Cyclone II JTAG Timing Parameters and Values
Symbol
Parameter
Min
Max
Unit
t_{J C P}
TCK clock period
40
—
ns
t_{J C H}
TCK clock high time
20
—
ns
t_{J C L}
TCK clock low time
20
—
ns
t_{J P S U}
JTAG port setup time (2)
5
—
ns
t_{J P H}
JTAG port hold time
10
—
ns
t_{J P C O}
JTAG port clock to output (2)
—
13
ns
t_{J P Z X}
JTAG port high impedance to valid output (2)
—
13
ns
t_{J P X Z}
JTAG port valid output to high impedance (2)
—
13
ns
t_{J S S U}
Capture register setup time (2)
5
—
ns
t_{J S H}
Capture register hold time
10
—
ns
t_{J S C O}
Update register clock to output
—
25
ns
t_{J S Z X}
Update register high impedance to valid output
—
25
ns
t_{J S X Z}
Update register valid output to high impedance
—
25
ns
Notes to Table 5–53:
(1) This information is preliminary.
(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For
1.8-V LVTTL/LVCMOS and 1.5-V LVCMOS, the JTAG port and capture register clock setup time is 3 ns and port
clock to output time is 15 ns.
f
1 Cyclone II devices must be within the first 17 devices in a JTAG
chain. All of these devices have the same JTAG controller. If any
of the Cyclone II devices are in the 18th position or after they will
fail configuration. This does not affect the SignalTap^® II logic
analyzer.
For more information on JTAG, refer to the IEEE 1149.1 (JTAG)
Boundary-Scan Testing for Cyclone II Devices chapter in the Cyclone II
Handbook.
Altera Corporation
February 2008
5–65
Cyclone II Device Handbook, Volume 1