EP2C20F256C8N Datasheet, PDF (170/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Timing Specifications
PLL Timing Specifications
Table 5–54 describes the Cyclone II PLL specifications when operating in
the commercial junction temperature range (0° to 85° C), the industrial
junction temperature range (–40° to 100° C), the automotive junction
temperature range (–40° to 125° C), and the extended temperature range
(–40° to 125° C). Follow the PLL specifications for –8 speed grade devices
when operating in the industrial, automotive, or extended temperature
range.
Table 5–54. PLL Specifications Note (1) (Part 1 of 2)
Symbol
Parameter
Min
f_{I N}
Input clock frequency (–6 speed grade)
10
Input clock frequency (–7 speed grade)
10
Input clock frequency (–8 speed grade)
10
f_{I N P F D}
PFD input frequency (–6 speed grade)
10
PFD input frequency (–7 speed grade)
10
PFD input frequency (–8 speed grade)
10
f_{I N D U T Y}
Input clock duty cycle
40
t_{I N J I T T E R} (5)
Input clock period jitter
—
f_{O U T _ E X T} (external
PLL output frequency (–6 speed grade)
10
clock output)
PLL output frequency (–7 speed grade)
10
PLL output frequency (–8 speed grade)
10
f_{O U T} (to global clock) PLL output frequency (–6 speed grade)
10
PLL output frequency (–7 speed grade)
10
PLL output frequency (–8 speed grade)
10
t_{O U T D U T Y}
Duty cycle for external clock output (when 45
set to 50%)
t_{J I T T E R} (p-p) (2)
Period jitter for external clock output
—
f_{O U T _ E X T} > 100 MHz
f_{O U T _ E X T} ≤100 MHz
—
t_{L O C K}
Time required to lock from end of device
—
configuration
t_{PLL_PSERR}
Accuracy of PLL phase shift
—
Typ
Max
Unit
—
(4)
MHz
—
(4)
MHz
—
(4)
MHz
—
402.5
MHz
—
402.5
MHz
—
402.5
MHz
—
60
%
200
—
ps
—
(4)
MHz
—
(4)
MHz
—
(4)
MHz
—
500
MHz
—
450
MHz
—
402.5
MHz
—
55
%
—
300
ps
—
30
mUI
—
100 (6)
μs
—
±60
ps
5–66
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008