EP2C20F256C8N Datasheet, PDF (379/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Altera Corporation
February 2007
Configuring Cyclone II Devices
The Enable user-supplied start-up clock (CLKUSR) option can be
turned on in the Quartus II software from the General tab of the Device
& Pin Options dialog box. Supplying a clock on CLKUSR does not affect
the configuration process. After all configuration data has been accepted
and CONF_DONE goes high, Cyclone II devices require 299 clock cycles to
initialize properly and support a CLKUSR f_MAX of 100 MHz.
1 If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
An optional INIT_DONE pin signals the end of initialization and the start
of user mode with a low-to-high transition. By default, the INIT_DONE
output is disabled. You can enable the INIT_DONE output by turning on
the Enable INIT_DONE output option in the Quartus II software. If you
use the INIT_DONE pin, an external 10-kΩ pull-up resistor pulls the pin
high when nCONFIG is low and during the beginning of configuration.
Once the optional bit to enable INIT_DONE is programmed into the
device (during the first frame of configuration data), the INIT_DONE pin
transitions low. When initialization is complete, the INIT_DONE pin is
released and pulled high. The MAX II device must be able to detect this
low-to-high transition, which signals the FPGA has entered user mode.
If you want to use the INIT_DONE pin as a user I/O pin, you should wait
for the maximum value of t_CD2UM (see Table 13–7) after the CONF_DONE
signal transitions high so to ensure the Cyclone II device has been
initialized properly and is in user mode.
Make sure the MAX II device does not drive the CONF_DONE signal low
during configuration, initialization, and before the device enters user
mode.
User Mode
When initialization is complete, the Cyclone II device enters user mode.
In user mode, the user I/O pins no longer have pull-up resistors and
function as assigned in your design.
To ensure DCLK and DATA0 are not left floating at the end of
configuration, the MAX II device must drive them either high or low,
which ever is convenient on your PCB. The Cyclone II device DATA0 pin
is not available as a user I/O pin after configuration.
When the FPGA is in user mode, you can initiate a reconfiguration by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin must be
low for at least 2 µs. When the nCONFIG transitions low, the Cyclone II
13–25
Cyclone II Device Handbook, Volume 1