EP2C20F256C8N Datasheet, PDF (362/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Active Serial Configuration (Serial Configuration Devices)
Figure 13–3. Single Device AS Configuration
V_CC (1)
V_CC (1)
V_CC (1)
10 kΩ
10 kΩ
Serial Configuration
Device
10 kΩ
Cyclone II FPGA
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
N.C. ⁽³⁾
DATA
DCLK
nCS
ASDI
GND
DATA0
V_CC
DCLK
nCSO
MSEL1
ASDO
MSEL0
(2)
GND
Notes to Figure 13–3:
(1) Connect the pull-up resistors to a 3.3-V supply.
(2) Cyclone II devices use the ASDO to ASDI path to control the configuration device.
(3) The nCEO pin can be left unconnected or used as a user I/O pin when it does not
feed another device’s nCE pin.
f
Upon power-up, the Cyclone II device goes through a POR. During POR,
the device resets, holds nSTATUS and CONF_DONE low, and tri-states all
user I/O pins. After POR, which typically lasts 100 ms, the Cyclone II
device releases nSTATUS and enters configuration mode when the
external 10-kΩ resistor pulls the nSTATUS pin high. Once the FPGA
successfully exits POR, all user I/O pins continue to be tri-stated.
Cyclone II devices have weak pull-up resistors on the user I/O pins
which are on before and during configuration.
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration are available in the DC Characteristics &
Timing Specifications chapter of the Cyclone II Device Handbook.
The configuration cycle consists of the reset, configuration, and
initialization stages.
13–8
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007