EP2C20F256C8N Datasheet, PDF (263/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

External Memory Interfaces
Cyclone II DDR
Memory Support
Overview
Table 9–1 shows the external memory interfaces supported in Cyclone II
devices.
Table 9–1. External Memory Support in Cyclone II Devices Note (1)
Memory Standard
I/O Standard
DDR SDRAM
DDR2 SDRAM
QDRII SRAM (4)
SSTL-2 class I (2)
SSTL-2 class II (2)
SSTL-18 class I (2)
SSTL-18 class II (3)
1.8-V HSTL class I (2)
1.8-V HSTL class II (3)
Maximum Bus
Width
72
72
72
72
36
36
Maximum Clock
Rate Supported
(MHz)
167
133
167
125
167
100
Maximum Data
Rate Supported
(Mbps)
333 (1)
267 (1)
333 (1)
250 (1)
667 (1)
400 (1)
Notes to Table 9–1:
(1) The data rate is for designs using the clock delay control circuitry.
(2) These I/O standards are supported on all the I/O banks of the Cyclone II device.
(3) These I/O standards are supported only on the I/O banks on the top and bottom of the Cyclone II device.
(4) For maximum performance, Altera recommends using the 1.8-V HSTL I/O standard because of higher I/O drive
strength. QDRII SRAM devices also support the 1.5-V HSTL I/O standard.
Cyclone II devices support the data strobe or read clock signal (DQS)
used in DDR SDRAM with the clock delay control circuitry that can shift
the incoming DQS signals to center them within the data window. To
achieve DDR operation, the DDR input and output registers are
implemented using the internal logic element (LE) registers. You should
use the altdqs and altdq megafunctions in the Quartus II software to
implement the DDR registers used for DQS and DQ signals, respectively.
Altera Corporation
February 2007
9–9
Cyclone II Device Handbook, Volume 1