EP2C20F256C8N Datasheet, PDF (262/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

External Memory Interface Standards
Figure 9–5. Data & Clock Relationship During a QDRII SRAM Report
C/K
Cn/Kn
Q
CQ
t_CO (2)
t_CLZ (3)
t_CO (2)
QA
QA + 1 QA + 2 QA + 3
t_DOH (2)
t_CHZ (3)
t_CQD (4)
CQn
t_CCQO (5)
t_CQOH (4)
t_CQD (4)
Notes to Figure 9–5:
(1) The timing parameter nomenclature is based on the Cypress QDRII SRAM data sheet for CY7C1313V18.
(2) t_{C O} is the data clock-to-out time and t_{D O H} is the data output hold time between burst.
(3) t_{C L Z} and t_{C H Z} are bus turn-on and turn-off times, respectively.
(4) t_{C Q D} is the skew between CQn and data edges.
(5) t_{C C Q O} and t_{C Q O H} are skew measurements between the C or C# clocks (or the K or K# clocks in single-clock mode)
and the CQ or CQn clocks.
When writing to QDRII SRAM devices, the write clock generates the data
while the K clock is 90° shifted from the write clock, creating a center-
aligned arrangement.
9–8
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007