EP2C20F256C8N Datasheet, PDF (236/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Memory Modes
f
outputs, respectively. When the output registers are bypassed, the new
data is available on the rising edge of the same clock cycle on which it was
written. See “Read-During- Write Operation at the Same Address” on
page 8–28 for waveforms and information on mixed-port
read-during-write mode.
Potential write contentions must be resolved external to the RAM because
writing to the same address location at both ports results in unknown
data storage at that location.
For the maximum synchronous write cycle time, refer to the Cyclone II
Device Family Data Sheet in volume 1 of the Cyclone II Device Handbook.
Figure 8–11 shows true dual-port timing waveforms for the write
operation at port A and the read operation at port B.
Figure 8–11. Cyclone II True Dual-Port Timing Waveforms
clk_a
wren_a
address_a
data_a (1)
q_a (synch)
q_a (asynch)
an-1
an
a0
din-1
din
din-2
din-1
din-1
din
a1
din
dout0
a2
dout0
dout1
a3
a4
a5
a6
din4
din5
din6
dout1
dout2
dout2
dout3
dout3
din4
din4
din5
clk_b
wren_b
address_b
bn
q_b (synch) doutn-2
b0
doutn-1
b1
doutn
b2
dout0
b3
dout1
q_b (asynch)
doutn-1
doutn
dout0
Note to Figure 8–11:
(1) The crosses in the data_a waveform during write indicate “don’t care.”
dout1
dout2
Shift Register Mode
Cyclone II memory blocks can implement shift registers for digital signal
processing (DSP) applications, such as finite impulse response (FIR)
filters, pseudo-random number generators, multi-channel filtering, and
auto-correlation and cross-correlation functions. These and other DSP
8–14
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008