EP2C20F256C8N Datasheet, PDF (270/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

DDR Memory Interface Pins
DQS pin to the DQ LE register does not necessarily match the delay from
the DQ pin to the DQ LE register. Therefore, you must adjust the clock
delay control circuitry to compensate for this difference in delays.
DQS Postamble
For external memory interfaces that use a bidirectional read strobe, such
as DDR and DDR2 SDRAM, the DQS signal is low before going to or
coming from the high-impedance state (see Figure 9–1). The state where
DQS is low just after high-impedance is called the preamble and the state
where DQS is low just before it goes to high-impedance is called the
postamble. There are preamble and postamble specifications for both
read and write operations in DDR and DDR2 SDRAM. If the Cyclone II
device or the DDR/DDR2 SDRAM device does not drive the DQ and
DQS pins, the signals go to a high-impedance state. Because a pull-up
resistor terminates both DQ and DQS to V_TT (1.25 V for SSTL-2 and 0.9 V
for SSTL-18), the effective voltage on the high-impedance line is either
1.25 V or 0.9 V. According to the JEDEC JESD8-9 specification for SSTL-2
I/O standard and the JESD8-15A specification for SSTL-18 I/O standard,
this is an indeterminate logic level, and the input buffer can interpret this
as either a logic high or logic low. If there is any noise on the DQS line, the
input buffer may interpret that noise as actual strobe edges.
Cyclone II devices have non-dedicated logic that can be configured to
prevent a false edge trigger at the end of the DQS postamble. Each
Cyclone II DQS signal is connected to postamble logic that consists of a D
flip flop (see Figure 9–9). This register is clocked by the shifted DQS
signal. Its input is connected to ground. The controller needs to include
extra logic to tell the reset signal to release the preset signal on the falling
DQS edge at the start of the postamble. This disables any glitches that
happen right after the postamble. This postamble logic is automatically
implemented by the Altera MegaCore DDR/DDR2 SDRAM Controller in
the LE register as part of the open-source datapath.
9–16
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007