EP2C20F256C8N Datasheet, PDF (273/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

External Memory Interfaces
Registers sync_reg_h and sync_reg_l synchronize the two data
streams to the rising edge of the resynchronization clock. Figure 9–12
shows examples of functional waveforms from a double data rate input
implementation.
Figure 9–12. DDR Input Functional Waveforms
DQS
Delay_DQS
DQ
Output of
Input Register A_I
Output of
Input Register B_I
Output of
Register C_I
resync_clk
Q0 Q1 Q2 Q3
Q1
Q0
Q0
Q3
Q2
Q2
dataout_h
Q1
Q3
dataout_l
Q0
Q2
The Cyclone II DDR input registers require you to invert the incoming
DQS signal to ensure proper data transfer. The altdq megafunction
automatically adds the inverter on the clock port of the DQ signals. As
shown in Figure 9–11, the inverted DQS signal’s rising edge clocks
register A_I, its falling edge clocks register B_I, and register C_I aligns the
data clocked by register B_I with register A_I on the inverted DQS signal’s
rising edge. In a DDR memory read operation, the last data coincides with
the falling edge of DQS signal. If you do not invert the DQS pin, you do
not get this last data because the register does not latch until the next
rising edge of the DQS signal.
Altera Corporation
February 2007
9–19
Cyclone II Device Handbook, Volume 1