EP2C20F256C8N Datasheet, PDF (297/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Selectable I/O Standards in Cyclone II Devices
Figure 10–13. 1.5-V HSTL Class I Termination
Output Buffer
V_TT = 0.75 V
Z = 50 Ω
50 Ω
V_REF = 0.75 V
Input Buffer
Figure 10–14. 1.5-V HSTL Class II Termination
V_TT = 0.75 V
V_TT = 0.75 V
Output Buffer
50 Ω
50 Ω
Z = 50 Ω
V_REF = 0.75 V
Input Buffer
1.5-V Pseudo-Differential HSTL Class I and II
The 1.5-V differential HSTL standard is formulated under EIA/JEDEC
Standard, EIA/JESD8-6: A 1.5V Output Buffer Supply Voltage Based
Interface Standard for Digital Integrated Circuits.
The 1.5-V differential HSTL specification is the same as the 1.5-V
single-ended HSTL specification. It is used for applications designed to
operate in the 0.0- to 1.5-V HSTL logic switching range, such as QDR
memory clock interfaces. Cyclone II devices support both input and
output levels. Refer to Figures 10–15 and 10–16 for details on the 1.5-V
differential HSTL termination.
Cyclone II devices do not support true 1.5-V differential HSTL standards.
Cyclone II devices support pseudo-differential HSTL outputs for
PLL_OUT pins and pseudo-differential HSTL inputs for clock pins.
Pseudo-differential inputs require an input reference voltage as opposed
to the true differential inputs. Refer to Table 10–1 on page 10–2 for
information about pseudo-differential HSTL.
Altera Corporation
February 2008
10–15
Cyclone II Device Handbook, Volume 1