EP2C20F256C8N Datasheet, PDF (195/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

PLLs in Cyclone II Devices
Figure 7–4. Phase Relationship between Cyclone II PLL Clocks in Normal
Mode
Phase Aligned
PLL inclk
PLL clock at the
register clock port
External PLL clock outputs (1)
Note to Figure 7–4:
(1) The external clock output can lead or lag the PLL clock signals.
Zero Delay Buffer Mode
In zero delay buffer mode, the clock signal on the PLL external clock
output pin (PLL<#>_OUT), fed by the c2 counter, is phase-aligned with
the PLL input clock pin for zero delay. If the c[1..0] ports drive internal
clock ports, there is a phase shift with respect to the input clock pin.
Figure 7–5 shows an example waveform of the PLL clocks’ phase
relationship in this mode.
Altera Corporation
February 2007
7–11
Cyclone II Device Handbook, Volume 1