EP2C20F256C8N Datasheet, PDF (429/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone II Devices
The IEEE Std. 1149.1 BST circuitry requires the following registers:
■ The instruction register determines the action to be performed and
the data register to be accessed.
■ The bypass register is a 1-bit-long data register that provides a
minimum-length serial path between TDI and TDO.
■ The boundary-scan register is a shift register composed of all the
boundary-scan cells of the device.
Figure 14–2 shows a functional model of the IEEE Std. 1149.1 circuitry.
Figure 14–2. IEEE Std. 1149.1 Circuitry
Instruction Register (1)
TDI
UPDATEIR
CLOCKIR
SHIFTIR
TDO
TMS
TCLK
TAP
Controller
UPDATEDR
CLOCKDR
SHIFTDR
Instruction Decode
Data Registers
Bypass Register
Boundary-Scan Register (1)
Device ID Register
ICR Registers
Note to Figure 14–2:
(1) For register lengths, see the device data sheet in the Configuration & Testing chapter in Volume 1 of the Cyclone II
Device Handbook.
IEEE Std. 1149.1 boundary-scan testing is controlled by a test access port
(TAP) controller. For more information on the TAP controller, see “IEEE
Std. 1149.1 BST Operation Control” on page 14–6. The TMS and TCK pins
Altera Corporation
February 2007
14–3
Cyclone II Device Handbook, Volume 1