EP2C20F256C8N Datasheet, PDF (271/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

External Memory Interfaces
Figure 9–9. Cyclone II DQS Postamble Circuitry Connection
DQ[7..0]
DQS'
DQS
Δt
DQS Programmable
Delay Chain
Circuitry
Capture Register
DQ
ENA
EnableN
Postamble
Logic
Capture Register
DQ
ENA
Capture Register
DQ
ENA
PRN
QD
CLRN
Reset
Global
Clock Network
Figure 9–10 shows the timing waveform for Figure 9–9. When the
postamble logic detects the falling DQS edge at the start of postamble, it
sends out a signal to disable the capture registers to prevent any
accidental latching.
Altera Corporation
February 2007
9–17
Cyclone II Device Handbook, Volume 1