EP2C20F256C8N Datasheet, PDF (189/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

PLLs in Cyclone II Devices
Figure 7–2. Cyclone II PLL Block Diagram
CLK0 (1)
CLK1
CLK2 (1)
CLK3
Manual Clock
Switchover
Select Signal
inclk0
f_IN
inclk1
Reference
Input Clock
f_REF = f_IN /n
÷n
PFD
up
down
Charge
Pump
f_FB
Loop
Filter
÷m
VCO Phase Selection
Selectable at Each
PLL Output Port
Post-Scale
Counters
8
f_VCO
8
VCO ÷k
(3)
8
÷c0
Global
Clock
Global
÷c1
Clock
÷c2
Global
(2)
Clock
PLL<#>_OUT
Lock Detect
& Filter
To I/O or
general routing
Notes to Figure 7–2:
(1) This input can be single-ended or differential. If you are using a differential I/O standard, then the design uses two
clock pins. LVDS input is supported via the secondary function of the dedicated clock pins. For example, the CLK0
pin’s secondary function is LVDSCLK1p and the CLK1 pin’s secondary function is LVDSCLK1n. Figure 7–2 shows
the possible clock input connections to PLL 1.
(2) This counter output is shared between a dedicated external clock output (PLL<#>_OUT) and the global clock
network.
(3) If the VCO post scale counter = 2, a 300- to 500-MHz internal VCO frequency is available.
The Cyclone II PLL supports up to three global clock outputs and one
dedicated external clock output. The output frequency to the global clock
network or dedicated external clock output is determined by using the
following equation:
m
f_{global/external} = f_{IN n × C}
f_IN is the clock input to the PLL and C is the setting on the c0, c1, or c2
counter.
The VCO frequency is determined in all cases by using the following
equation:
m
f_VCO = f_{IN n}
Altera Corporation
February 2007
7–5
Cyclone II Device Handbook, Volume 1