EP2C20F256C8N Datasheet, PDF (174/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Duty Cycle Distortion
Table 5–55. Maximum DCD for Single Data Outputs (SDR) on Row I/O
Pins Notes (1), (2) (Part 2 of 2)
Row I/O Output Standard
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential HSTL-18 Class I
Differential HSTL-15 Class I
LVDS
Simple RSDS
Mini LVDS
PCI
PCI-X
C6
C7
C8
Unit
60
90
90
ps
65
75
75
ps
90
165
165
ps
85
155
155
ps
145
145
205
ps
60
60
60
ps
60
60
60
ps
60
60
60
ps
195
255
255
ps
195
255
255
ps
Notes to Table 5–55:
(1) The DCD specification is characterized using the maximum drive strength
available for each I/O standard.
(2) Numbers are applicable for commercial, industrial, and automotive devices.
Here is an example for calculating the DCD as a percentage for an SDR
output on a row I/O on a –6 device:
If the SDR output I/O standard is SSTL-2 Class II, the maximum DCD is
65 ps (refer to Table 5–55). If the clock frequency is 167 MHz, the clock
period T is:
T = 1/ f = 1 / 167 MHz = 6 ns = 6000 ps
To calculate the DCD as a percentage:
(T/2 – DCD) / T = (6000 ps/2 – 65 ps) / 6000 ps = 48.91% (for low
boundary)
(T/2 + DCD) / T = (6000 ps/2 + 65 ps) / 6000ps = 51.08% (for high
boundary
Table 5–56. Maximum DCD for SDR Output on Column I/O Notes (1), (2)
(Part 1 of 2)
Column I/O Output Standard
LVCMOS
LVTTL
C6
C7
C8
Unit
195
285
285
ps
210
305
305
ps
5–70
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008