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EP2C20F256C8N Datasheet, PDF (73/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1 | |||
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Cyclone II Architecture
Table 2â15. Cyclone II DQS & DQ Bus Mode Support (Part 2 of 2) Note (1)
Device
EP2C35
EP2C50
EP2C70
Package
484-pin FineLine BGA
672-pin FineLine BGA
484-pin FineLine BGA
672-pin FineLine BGA
672-pin FineLine BGA
896-pin FineLine BGA
Number of Ã8
Groups
16 (4)
20 (4)
16 (4)
20 (4)
20 (4)
20 (4)
Number of Ã9 Number of Ã16 Number of Ã18
Groups (5), (6) Groups Groups (5), (6)
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Notes to Table 2â15:
(1) Numbers are preliminary.
(2) EP2C5 and EP2C8 devices in the 144-pin TQFP package do not have any DQ pin groups in I/O bank 1.
(3) Because of available clock resources, only a total of 6 DQ/DQS groups can be implemented.
(4) Because of available clock resources, only a total of 14 DQ/DQS groups can be implemented.
(5) The Ã9 DQS/DQ groups are also used as Ã8 DQS/DQ groups. The Ã18 DQS/DQ groups are also used as Ã16
DQS/DQ groups.
(6) For QDRI implementation, if you connect the D ports (write data) to the Cyclone II DQ pins, the total available Ã9
DQS /DQ and Ã18 DQS/DQ groups are half of that shown in Table 2â15.
You can use any of the DQ pins for the parity pins in Cyclone II devices.
The Cyclone II device family supports parity in the Ã8/Ã9, and Ã16/Ã18
mode. There is one parity bit available per eight bits of data pins.
The data mask, DM, pins are required when writing to DDR SDRAM and
DDR2 SDRAM devices. A low signal on the DM pin indicates that the
write is valid. If the DM signal is high, the memory masks the DQ signals.
In Cyclone II devices, the DM pins are assigned and are the preferred
pins. Each group of DQS and DQ signals requires a DM pin.
When using the Cyclone II I/O banks to interface with the DDR memory,
at least one PLL with two clock outputs is needed to generate the system
and write clock. The system clock is used to clock the DQS write signals,
commands, and addresses. The write clock is shifted by â90° from the
system clock and is used to clock the DQ signals during writes.
Figure 2â27 illustrates DDR SDRAM interfacing from the I/O through
the dedicated circuitry to the logic array.
Altera Corporation
February 2007
2â47
Cyclone II Device Handbook, Volume 1
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