EP2C20F256C8N Datasheet, PDF (200/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Hardware Features
Phase-Shifting Implementation
Cyclone II devices use fine or coarse phase shifts for clock delays because
they are more efficient than delay elements and are independent of
process, voltage, and temperature.
Phase shift is implemented by using a combination of the VCO phase
output and the counter starting time. The VCO phase taps and counter
starting time are independent of process, voltage, and temperature. The
VCO phase taps allow you to phase shift the Cyclone II PLL output clocks
with fine resolution. The counter starting time allows you to phase shift
the Cyclone II PLL output clocks with coarse resolution.
Fine-resolution phase shifting is implemented using any of the eight VCO
phases for the output counters (c[2..0]) or the feedback counter (m)
reference clock. This provides the finest resolution for phase shift. The
minimum delay time that may be inserted using this method is defined
by the equation:
1
1
n
Δt_FINE =
8 ^{tVCO =}
=
8 × f_VCO
8 × m × f_IN
f_IN is input reference clock frequency.
For example, if f_IN is 100 MHz, n is 1 and m is 8, then f_VCO is 800 MHz and
Δt is 156.25 ps. This delay time is defined by the PLL operating frequency
which is governed by the reference clock and the counter settings.
The second way to implement phase shifts is by delaying the start of the
m and post-scale counters for a predetermined number of counter clocks.
This delay time may be expressed as:
S − 1 (S − 1) × n
Δt_COARSE = _fVCO =
m × f_IN
where S is the value set for the counter starting time. The counter starting
time is called the Initial setting in the PLL Usage section of the
compilation report in the Quartus II software.
Figure 7–8 shows an example of delay insertion using these two methods.
The eight phases from the VCO are shown and labeled for reference. For
this example, OUTCLK0 is based off the 0° phase from the VCO and has
the S value for the counter set to 1. It is divided by 4 (two VCO clocks for
high time and two VCO clocks for low time). OUTCLK1 is based off the
135° phase tap from the VCO and also has the S value for the counter set
to 1. It is also divided by 4. In this case, the two clocks are offset by three
7–16
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007