EP2C20F256C8N Datasheet, PDF (201/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

PLLs in Cyclone II Devices
Δt_FINE periods. OUTCLK2 is based off the 0° phase from the VCO but has
the S value for the counter set to 3. This creates a delay of two Δt_COARSE
periods.
Figure 7–8. Cyclone II PLL Phase Shifting using VCO Phase Output & Counter Delay Time
1/8 t_VCO
t_VCO
0˚
45˚
90˚
135˚
180˚
225˚
270˚
315˚
OUTCLK0
OUTCLK1
OUTCLK2
t_d0-1
t_d0-2
Altera Corporation
February 2007
Control Signals
The four control signals in Cyclone II PLLs (pllena, areset, pfdena,
and locked) control PLL operation.
pllena
The PLL enable signal, pllena, enables and disables the PLL. You can
either enable/disable a single PLL (by connecting pllena port
independently) or multiple PLLs (by connecting pllena ports together).
The pllena signal is an active-high signal. When pllena is low, the PLL
clock output ports are driven by GND and the PLL loses lock. All PLL
counters, including gated lock counter return to default state. When
pllena transitions high, the PLL relocks and resynchronizes to the input
clock. In Cyclone II devices, the pllena port can be fed by an LE output
or any general-purpose I/O pin. There is no dedicated pllena pin. This
increases flexibility since each PLL can have its own pllena control
circuitry or all PLLs can share the same pllena circuitry. The pllena
signal is optional. When it is not enabled in the Quartus II software, the
port is internally tied to V_CC.
7–17
Cyclone II Device Handbook, Volume 1