EP2C20F256C8N Datasheet, PDF (315/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Selectable I/O Standards in Cyclone II Devices
pin+11
Σ I_PIN < 240mA per power pair
pin
In all cases listed above, the Quartus II software generates an error
message for illegally placed pads.
Table 10–12 shows the I/O standard DC current specification.
Table 10–12. Cyclone II I/O Standard DC Current Specification (Preliminary) (Part 1 of 2)
I/O Standard
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
1.8-V HSTL class I
1.8-V HSTL class II
1.5-V HSTL class I
1.5-V HSTL class II
Differential SSTL-2 class I (3)
Differential SSTL-2 class II (3)
Differential SSTL-18 class I (3)
Differential SSTL-18 class II (3)
1.8-V differential HSTL class I (3)
1.8-V differential HSTL class II (3)
1.5-V differential HSTL class I (3)
I_PIN (mA)
Top and Bottom Banks
(1)
(1)
(1)
(1)
(1)
Not supported
Not supported
12 (2)
24 (2)
12 (2)
8 (2)
12 (2)
20 (2)
12 (2)
18 (2)
8.1 (4)
16.4 (4)
6.7 (4)
13.4 (4)
8 (4)
16 (4)
8 (4)
Side Banks
(1)
(1)
(1)
(1)
(1)
1.5
1.5
12 (2)
20 (2)
12 (2)
Not supported
12 (2)
Not supported
10 (2)
Not supported
Altera Corporation
February 2008
10–33
Cyclone II Device Handbook, Volume 1