EP2C20F256C8N Datasheet, PDF (196/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Clock Feedback Modes
Figure 7–5. Phase Relationship between Cyclone II PLL Clocks in Zero Delay
Buffer Mode
Phase Aligned
PLL Reference
Clock at the Input Pin
PLL clock at the
register clock port (1)
External PLL clock
outputs at the Output Pin
Note to Figure 7–5:
(1) The internal clock output(s) can lead or lag the external PLL clock output
(PLL<#>_OUT) signals.
1 Altera recommends using the same I/O standard on the input
and output clocks when using the Cyclone II PLL in zero delay
buffer mode.
No Compensation Mode
In no compensation mode, the PLL does not compensate for any clock
networks, which leads to better jitter performance. Because the clock
feedback into the PFD does not pass through as much circuitry, both the
PLL internal clock outputs and external clock outputs are phase shifted
with respect to the PLL clock input. Figure 7–6 shows an example
waveform of the PLL clocks’ phase relationship in this mode.
7–12
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007