EP2C20F256C8N Datasheet, PDF (424/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Conclusion
Table 13–13 describes the dedicated JTAG pins. JTAG pins must be kept
stable before and during configuration to prevent accidental loading of
JTAG instructions. The TCK pin has a weak internal pull-down resistor
and the TDI and TMS JTAG input pins have weak internal pull-up
resistors.
Table 13–13. Dedicated JTAG Pins
Pin Name User Mode Pin Type
TDI
N/A
Input
TDO
N/A
Output
TMS
N/A
Input
TCK
N/A
Input
Description
Serial input pin for instructions as well as test and programming
data. Data is shifted in on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG
circuitry can be disabled by connecting this pin to V_CC.
The input buffer on this pin supports hysteresis using Schmitt
trigger circuitry.
Serial data output pin for instructions as well as test and
programming data. Data is shifted out on the falling edge of
TCK. The pin is tri-stated if data is not being shifted out of the
device.
If the JTAG interface is not required on the board, the JTAG
circuitry can be disabled by leaving this pin unconnected.
Input pin that provides the control signal to determine the
transitions of the TAP controller state machine. Transitions
within the state machine occur on the rising edge of TCK.
Therefore, TMS must be set up before the rising edge of TCK.
TMS is evaluated on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG
circuitry can be disabled by connecting this pin to V_CC.
The input buffer on this pin supports hysteresis using Schmitt
trigger circuitry.
The clock input to the BST circuitry. Some operations occur at
the rising edge, while others occur at the falling edge.
If the JTAG interface is not required on the board, the JTAG
circuitry can be disabled by connecting this pin to GND.
The input buffer on this pin supports hysteresis using Schmitt
trigger circuitry.
Conclusion
Cyclone II devices can be configured in AS, PS or JTAG configuration
schemes to fit your system's need. The AS configuration scheme
supported by Cyclone II devices can now operate at a higher DCLK
13–70
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007