EP2C20F256C8N Datasheet, PDF (194/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Clock Feedback Modes
Table 7–6. I/O Standards Supported for Cyclone II PLLs (Part 2 of 2)
I/O Standard
SSTL-25 class II
RSDS/mini-LVDS (4)
Input
inclk
v
Output
lock
pll_out
v
v
v
v
Notes to Table 7–6:
(1) The PCI-X I/O standard is supported only on side I/O pins.
(2) Differential SSTL and HSTL outputs are only supported on the PLL<#>_OUT pins.
(3) These I/O standards are only supported on top and bottom I/O pins.
(4) The RSDS and mini-LVDS pins are only supported on output pins.
Clock Feedback
Modes
Cyclone II PLLs support four clock feedback modes: normal mode, zero
delay buffer mode, no compensation mode, and source synchronous
mode. Cyclone II PLLs do not have support for external feedback mode.
All the supported clock feedback modes allow for multiplication and
division, phase shifting, and programmable duty cycle. The phase
relationships shown in the waveforms in Figures 7–4 through 7–6 are for
the default (zero degree) phase shift setting. Changing the phase-shift
setting changes the relationships between the output clocks from the PLL.
Normal Mode
In normal mode, the PLL phase-aligns the input reference clock with the
clock signal at the ports of the registers in the logic array I/O registers to
compensate for the internal global clock network delay. Use the altpll
megafunction in the Quartus II software to define which internal clock
output from the PLL (c0, c1, or c2) to compensate for.
If an external clock output pin (PLL<#>_OUT) is used in this mode, there
is a phase shift with respect to the clock input pin. Similarly, if the internal
PLL clock outputs are used to drive general-purpose I/O pins, there is be
phase shift with respect to the clock input pin.
Figure 7–4 shows an example waveform of the PLL clocks’ phase
relationship in this mode.
7–10
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007