EP2C20F256C8N Datasheet, PDF (274/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

DDR Memory Interface Pins
Figure 9–13 shows waveforms of the circuit shown in Figure 9–11. The
first set of waveforms in Figure 9–13 shows the edge-aligned relationship
between the DQ and DQS signals at the Cyclone II device pins. The
second set of waveforms in Figure 9–13 shows what happens if the
shifted DQS signal is not inverted. In this case, the last data, Q_n, does not
get latched into the logic array as DQS goes to tri-state after the read
postamble time. The third set of waveforms in Figure 9–13 shows a
proper read operation with the DQS signal inverted after the 90° shift.
The last data, Q_n, does get latched. In this case the outputs of register A_I
and register C_I, which correspond to dataout_h and dataout_l ports,
are now switched because of the DQS inversion. Register A_I, register B_I,
and register C_I refer to the nomenclature in Figure 9–11.
Figure 9–13. DQ Captures With Noninverted & Inverted Shifted DQS
DQ & DQS Signals
DQ at the Pin Qn _{- 2} Qn _{- 1}
Qn
DQS at the Pin
Shifted DQS Signal is Not Inverted
DQS Shifted by 90˚
Output of Register AI (dataout_h)
Output of Register BI
Output of Register CI (dataout_l)
Shifted DQS Signal is Inverted
DQS Inverted and
Shifted by 90˚
Output of Register AI
(dataout_h)
Output of Register BI
Output of Register CI
(dataout_I)
Qn _{- 1}
Qn _{- 2}
Qn _{- 2}
Qn _{- 2}
Qn _{- 1}
Qn _{- 3}
Qn
Qn
Qn _{- 1}
9–20
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007