EP2C20F256C8N Datasheet, PDF (335/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

High-Speed Differential Interfaces in Cyclone II Devices
Figure 11–12. Differential SSTL Class I Interface
VTT
VTT
Output Buffer
25 Ω
25 Ω
Z0 = 50 Ω
50 Ω
Z0 = 50 Ω
50 Ω _Receiver
Figure 11–13. Differential SSTL Class II Interface
VTT
VTT
VTT
VTT
Output Buffer
25 Ω
50 Ω
25 Ω
50 Ω
Z0 = 50 Ω
50 Ω
Z0 = 50 Ω
50 Ω
Receiver
f
Differential HSTL Support in Cyclone II Devices
The differential HSTL AC and DC specifications are the same as the HSTL
single-ended specifications. The differential HSTL I/O standard is
available on the GCLK pins only, treating differential inputs as two single-
ended HSTL, and only decoding one of them. The differential HSTL
output I/O standard is only supported at the PLLCLKOUT pins using two
single-ended HSTL output buffers with the second output programmed
as inverted. The standard requires two differential inputs with an
external termination voltage (V_TT) of 0.5 × V_CCIO to which termination
resistors are connected.
For the HSTL signaling characteristics, see the DC Characteristics &
Timing Specifications chapter and the Selectable I/O Standards in Cyclone II
Devices chapter in Volume 1 of the Cyclone II Device Handbook.
Altera Corporation
February 2007
11–13
Cyclone II Device Handbook, Volume 1