EP2C20F256C8N Datasheet, PDF (416/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

JTAG Configuration
feature. To use this feature successfully, set the MSEL[1..0] pins of the
master Cyclone II device to select the AS configuration scheme or fast AS
configuration scheme (see Table 13–1).
1 The Quartus II software version 4.1 and higher supports serial
configuration device ISP through an FPGA JTAG interface using
a JIC file.
The serial configuration device in-system programming through the
Cyclone II JTAG interface has three stages, which are described in the
following sections.
Loading the Serial Flash Loader Design
The serial flash loader design is a design inside the Cyclone II device that
bridges the JTAG interface and AS interface inside the Cyclone II device
using glue logic.
The intelligent host uses the JTAG interface to configure the master
Cyclone II device with a serial flash loader design. The serial flash loader
design allows the master Cyclone II device to control the access of four
serial configuration device pins, also known as the Active Serial Memory
Interface (ASMI) pins, through the JTAG interface. The ASMI pins are the
serial clock input (DCLK), serial data output (DATA), AS data input (ASDI),
and an active-low chip select (nCS) pins.
If you configure a master Cyclone II device with a serial flash loader
design, the master Cyclone II device can enter user mode even though the
slave devices in the multiple device chain are not being configured. The
master Cyclone II device can enter user mode with a serial flash loader
design even though the CONF_DONE signal is externally held low by the
other slave devices in chain. Figure 13–25 shows the JTAG configuration
of a single Cyclone II device with a serial flash loader design.
13–62
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007