EP2C20F256C8N Datasheet, PDF (277/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

External Memory Interfaces
Figure 9–16. Bidirectional DDR Implementation for DDR Memory Interfaces Note (1)
OE
datain_h
LE
Register
data1
Output Register A_O
data0 _sel
datain_l
LE
Register
TRI
Output Register B_O
outclk
dataout_h
LE
LE
DQ
Register
Register
sync_reg_h
Input Register A_I
dataout_l
resynch_clk
V_CC
LE
Register
sync_reg_l
LE
Register
GND
LE
Register
LE
neg_reg_out
LE
Register
Register
Register C_I
Input Register B_I
TRI
sel
Clock Delay
Control Circuitry
t
DQS
Note to Figure 9–16:
(1) You can use the altdq and altdqs megafunctions to generate the DQ and DQS signals.
Figure 9–17 shows example waveforms from a bidirectional DDR
implementation.
Altera Corporation
February 2007
9–23
Cyclone II Device Handbook, Volume 1