EP2C20F256C8N Datasheet, PDF (101/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Hot Socketing & Power-On Reset
Figure 4–2. Transistor Level Diagram of FPGA Device I/O Buffers
Logic Array
Signal
V_PAD
(1)
(2)
V_CCIO
n+
n+
p-well
p+
p+
n+
n-well
p-substrate
Notes to Figure 4–2:
(1) This is the logic array signal or the larger of either the V_CCIO or V_PAD signal.
(2) This is the larger of either the V_CCIO or V_PAD signal.
Power-On Reset
Circuitry
Cyclone II devices contain POR circuitry to keep the device in a reset state
until the power supply voltage levels have stabilized during power-up.
The POR circuit monitors the V_CCINT voltage levels and tri-states all user
I/O pins until the V_CC reaches the recommended operating levels. In
addition, the POR circuitry also monitors the V_CCIO level of the two I/O
banks that contains configuration pins (I/O banks 1 and 3 for EP2C5 and
EP2C8, I/O banks 2 and 6 for EP2C15A, EP2C20, EP2C35, EP2C50, and
EP2C70) and tri-states all user I/O pins until the V_CC reaches the
recommended operating levels.
After the Cyclone II device enters user mode, the POR circuit continues to
monitor the V_CCINT voltage level so that a brown-out condition during
user mode can be detected. If the V_CCINT voltage sags below the POR trip
point during user mode, the POR circuit resets the device. If the V_CCIO
voltage sags during user mode, the POR circuit does not reset the device.
"Wake-up" Time for Cyclone II Devices
In some applications, it may be necessary for a device to wake up very
quickly in order to begin operation. The Cyclone II device family offers
the Fast-On feature to support fast wake-up time applications. Devices
that support the Fast-On feature are designated with an “A” in the
ordering code and have stricter power up requirements compared to non-
A devices.
Altera Corporation
February 2007
4–5
Cyclone II Device Handbook, Volume 1