Z8F0113HJ005EG Datasheet, PDF (98/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
83
7. Counting begins on the first appropriate transition of the Timer Input signal. No inter-
rupt is generated by this first edge.
In CAPTURE/COMPARE Mode, the elapsed time from timer start to capture event can be
calculated using the following equation:
Capture
Elapsed
Time
(s)
=
-^--^C-----^a----^p---^t--^u----^r--^e------^V----^a----^l-^u----^e------^–-----^S----^t--^a----^r--^t----^V----^a----^l-^u----^e----^----^-----^P----^r--^e----^s---^c----^a---^l--^e--
System Clock Frequency (Hz)
Reading the Timer Count Values
The current count value in the timers can be read while counting (enabled). This capability
has no effect on timer operation. When the timer is enabled and the Timer High Byte Reg-
ister is read, the contents of the Timer Low Byte register are placed in a holding register. A
subsequent read from the Timer Low Byte register returns the value in the holding register.
This operation allows accurate reads of the full 16-bit timer count value while enabled.
When the timers are not enabled, a read from the Timer Low Byte register returns the
actual value in the counter.
Timer Pin Signal Operation
Timer Output is a GPIO port pin alternate function. The Timer Output is toggled every
time the counter is reloaded.
The timer input can be used as a selectable counting source. It shares the same pin as the
complementary timer output. When selected by the GPIO Alternate Function registers,
this pin functions as a timer input in all modes except for the DUAL PWM OUTPUT
mode. For this mode, there is no timer input available.
Timer Control Register Definitions
This section defines the features of the following Timer Control registers.
Timer 0–1 High and Low Byte Registers: see page 83
Timer Reload High and Low Byte Registers: see page 84
Timer 0–1 PWM High and Low Byte Registers: see page 86
Timer 0–1 Control Registers: see page 86
Timer 0–1 High and Low Byte Registers
The Timer 0–1 High and Low Byte (TxH and TxL) registers (Table 51 and Table 52) con-
tain the current 16-bit timer count value. When the timer is enabled, a read from TxH
PS024315-1011
PRELIMINARY
Timer Control Register Definitions