Z8F0113HJ005EG Datasheet, PDF (105/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
90
Bit
[6]
TPOL
(cont’d.)
Description (Continued)
COMPARATOR COUNTER Mode
When the timer is disabled, the Timer Output signal is set to the value of this bit. When the
timer is enabled, the Timer Output signal is complemented upon timer reload.
[5:3]
PRES
[2:0]
TMODE
Caution: When the Timer Output alternate function TxOUT on a GPIO port pin is enabled,
TxOUT changes to whatever state the TPOL bit is in. The timer does not need to be enabled
for that to happen. Also, the port data direction sub register is not needed to be set to output on
TxOUT. Changing the TPOL bit with the timer enabled and running does not immediately
change the TxOUT.
Prescale Value
The timer input clock is divided by 2^PRES, where PRES can be set from 0 to 7. The prescaler is
reset each time the timer is disabled. This reset ensures proper clock division each time the
timer is restarted.
000 = Divide by 1.
001 = Divide by 2.
010 = Divide by 4.
011 = Divide by 8.
100 = Divide by 16.
101 = Divide by 32.
110 = Divide by 64.
111 = Divide by 128.
Timer Mode
This field, along with the TMODEHI bit in TxCTL0 Register, determines the operating mode of
the timer. TMODEHI is the most significant bit of the timer mode selection value.
0000 = ONE-SHOT Mode.
0001 = CONTINUOUS Mode.
0010 = COUNTER Mode.
0011 = PWM SINGLE OUTPUT Mode.
0100 = CAPTURE Mode.
0101 = COMPARE Mode.
0110 = GATED Mode.
0111 = CAPTURE/COMPARE Mode.
1000 = PWM DUAL OUTPUT Mode.
1001 = CAPTURE RESTART Mode.
1010 = COMPARATOR COUNTER Mode.
PS024315-1011
PRELIMINARY
Timer Control Register Definitions