Z8F0113HJ005EG Datasheet, PDF (59/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
44
Table 23. Port A–C Alternate Function Subregisters (PxAF)
Bit
Field
RESET
R/W
Address
7
6
5
4
3
2
1
0
AF7
AF6
AF5
AF4
AF3
AF2
AF1
AF0
00H (Ports A–C); 04H (Port A of 8-pin device)
R/W
If 02H in Port A–C Address Register, accessible through the Port A–C Control Register
Bit
Description
[7:0]
AFx
Port Alternate Function enabled
0 = The port pin is in NORMAL Mode and the DDx bit in the Port A–C Data Direction Subregis-
ter determines the direction of the pin.
1 = The alternate function selected through Alternate Function Set subregisters is enabled.
Port pin operation is controlled by the alternate function.
Note: x indicates the specific GPIO port pin number (7–0).
Bit
Field
RESET
R/W
Address
Port A–C Output Control Subregisters
The Port A–C Output Control Subregister (Table 24) is accessed through the Port A–C
Control Register by writing 03H to the Port A–C Address Register. Setting the bits in the
Port A–C Output Control subregisters to 1 configures the specified port pins for open-
drain operation. These subregisters affect the pins directly and, as a result, alternate func-
tions are also affected.
Table 24. Port A–C Output Control Subregisters (PxOC)
7
6
5
4
3
2
1
0
POC7 POC6 POC5 POC4 POC3 POC2 POC1 POC0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 03H in Port A–C Address Register, accessible through the Port A–C Control Register
Bit
Description
[7:0]
POCx
Port Output Control
These bits function independently of the alternate function bit and always disable the drains if
set to 1.
0 = The drains are enabled for any output mode (unless overridden by the alternate function).
1 = The drain of the associated pin is disabled (open-drain mode).
Note: x indicates the specific GPIO port pin number (7–0).
PS024315-1011
PRELIMINARY
GPIO Control Register Definitions