Z8F0113HJ005EG Datasheet, PDF (85/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
70
Architecture
Figure 9 displays the architecture of the timers.
Data
Bus
Block
Control
System
Clock
Timer
Input
Timer
Control
Timer Block
Gate
Input
Capture
Input
16-Bit
Reload Register
16-Bit Counter
with Prescaler
Interrupt,
PWM,
and
Timer Output
Control
16-Bit
PWM/Compare
Figure 9. Timer Block Diagram
Timer
Interrupt
Timer
Output
Timer
Output
Complement
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value
0001H into the Timer Reload High and Low Byte registers and setting the prescale value
to 1. Maximum time-out delay is set by loading the value 0000H into the Timer Reload
High and Low Byte registers and setting the prescale value to 128. If the Timer reaches
FFFFH, the timer rolls over to 0000H and continues counting.
Timer Operating Modes
The timers can be configured to operate in the following modes:
ONE-SHOT Mode
In ONE-SHOT Mode, the timer counts up to the 16-bit reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. Upon reaching
the reload value, the timer generates an interrupt and the count value in the Timer High
and Low Byte registers is reset to 0001H. The timer is automatically disabled and stops
counting.
PS024315-1011
PRELIMINARY
Architecture