Z8F0113HJ005EG Datasheet, PDF (42/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
27
The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H
and loads that value into the Program Counter. Program execution begins at the Reset vec-
tor address. Following Stop Mode Recovery, the STOP bit in the Watchdog Timer Control
Register is set to 1. Table 11 lists the Stop Mode Recovery sources and resulting actions.
The section following the table provides more detailed information about each of the Stop
Mode Recovery sources.
Table 11. Stop Mode Recovery Sources and Resulting Action
Operating Mode Stop Mode Recovery Source
Action
STOP Mode
Watchdog Timer time-out when configured Stop Mode Recovery
for Reset
Watchdog Timer time-out when configured Stop Mode Recovery followed by interrupt
for interrupt
(if interrupts are enabled)
Data transition on any GPIO port pin
Stop Mode Recovery
enabled as a Stop Mode Recovery source
Assertion of external RESET Pin
System Reset
Debug Pin driven Low
System Reset
Stop Mode Recovery Using Watchdog Timer Time-Out
If the Watchdog Timer times out during STOP Mode, the device undergoes a Stop Mode
Recovery sequence. In the Watchdog Timer Control Register, the WDT and STOP bits are set
to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and Z8
Encore! XP F0823 Series device is configured to respond to interrupts, the eZ8 CPU services
the Watchdog Timer interrupt request following the normal Stop Mode Recovery sequence.
Stop Mode Recovery Using a GPIO Port Pin Transition
Each of the GPIO port pins can be configured as a Stop Mode Recovery input source. On
any GPIO pin enabled as a Stop Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery.
Note: The SMR pulses shorter than specified does not trigger a recovery. When this happens, the
STOP bit in the Reset Status (RSTSTAT) Register is set to 1.
Caution: In STOP Mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input
Data registers record the port transition only if the signal stays on the port pin through the
end of the Stop Mode Recovery delay. As a result, short pulses on the port pin can initiate
Stop Mode Recovery without being written to the Port Input Data Register or without ini-
tiating an interrupt (if enabled for that pin).
PS024315-1011
PRELIMINARY
Stop Mode Recovery