Z8F0113HJ005EG Datasheet, PDF (185/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
170
Caution: Unintentional accesses to the Oscillator Control Register can actually stop the chip by
switching to a non-functioning oscillator. To prevent this condition, the oscillator control
block employs a register unlocking/locking scheme.
OSC Control Register Unlocking/Locking
To write to the Oscillator Control Register, unlock it by making two writes to the OSC-
CTL Register with the values E7H followed by 18H. A third write to the OSCCTL Regis-
ter changes the value of the actual register and returns the register to a locked state. Any
other sequence of Oscillator Control Register writes has no effect. The values written to
unlock the register must be ordered correctly, but are not necessarily consecutive. It is pos-
sible to write to or read from other registers within the unlocking/locking operation.
When selecting a new clock source, the primary oscillator failure detection circuitry and
the Watchdog Timer oscillator failure circuitry must be disabled. If POFEN and WOFEN
are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a
failure of either oscillator. The Failure detection circuitry can be enabled anytime after a
successful write of OSCSEL in the Oscillator Control Register.
The internal precision oscillator is enabled by default. If the user code changes to a differ-
ent oscillator, it is appropriate to disable the IPO for power savings. Disabling the IPO
does not occur automatically.
Clock Failure Detection and Recovery
Should an oscillator or timer fail, there are methods of recovery, as this section describes.
Primary Oscillator Failure
Z8 Encore! XP F0823 Series devices can generate non-maskable interrupt-like events
when the primary oscillator fails. To maintain system function in this situation, the clock
failure recovery circuitry automatically forces the Watchdog Timer oscillator to drive the
system clock. The Watchdog Timer oscillator must be enabled to allow the recovery.
Although this oscillator runs at a much slower speed than the original system clock, the
CPU continues to operate, allowing execution of a clock failure vector and software rou-
tines that either remedy the oscillator failure or issue a failure alert. This automatic switch-
over is not available if the Watchdog Timer is the primary oscillator. It is also unavailable
if the Watchdog Timer oscillator is disabled, though it is not necessary to enable the
Watchdog Timer reset function outlined in the the Watchdog Timer section on page 91.
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1 kHz ±50%. If an external signal is selected as the system oscillator, it is pos-
sible that a very slow but non-failing clock can generate a failure condition. Under these
PS024315-1011
PRELIMINARY
Operation