Z8F0113HJ005EG Datasheet, PDF (41/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
26
clock and reset signals, the required reset duration can be as short as three clock periods
and as long as four. A reset pulse three clock cycles in duration might trigger a reset; a
pulse four cycles in duration always triggers a reset.
While the RESET input pin is asserted Low, the Z8 Encore! XP F0823 Series devices
remain in the Reset state. If the RESET pin is held Low beyond the System Reset time-
out, the device exits the Reset state on the system clock rising edge following RESET pin
deassertion. Following a System Reset initiated by the external RESET pin, the EXT sta-
tus bit in the WDT Control (WDTCTL) register is set to 1.
External Reset Indicator
During System Reset or when enabled by the GPIO logic (see the Port A–C Control Reg-
isters section on page 42), the RESET pin functions as an open-drain (active Low) reset
mode indicator in addition to the input functionality. This reset output feature allows an Z8
Encore! XP F0823 Series device to reset other components to which it is connected, even
if that reset is caused by internal sources such as POR, VBO, or WDT events.
After an internal reset event occurs, the internal circuitry begins driving the RESET pin
Low. The RESET pin is held Low by the internal circuitry until the appropriate delay
listed in Table 9 has elapsed.
On-Chip Debugger Initiated Reset
A POR is initiated using the On-Chip Debugger by setting the RST bit in the OCD Control
Register. The OCD block is not reset but the rest of the chip goes through a normal system
reset. The RST bit automatically clears during the System Reset. Following the System
Reset, the POR bit in the Reset Status (RSTSTAT) Register is set.
Stop Mode Recovery
The device enters into STOP Mode when eZ8 CPU executes a STOP instruction. For more
details about STOP Mode, see the Low-Power Modes section on page 30. During Stop
Mode Recovery, the CPU is held in reset for 66 IPO cycles if the crystal oscillator is dis-
abled or 5000 cycles if it is enabled. The SMR delay also included the time required to
start up the IPO.
Stop Mode Recovery does not affect on-chip registers other than the Watchdog Timer
Control Register (WDTCTL) and the Oscillator Control Register (OSCCTL). After any
Stop Mode Recovery, the IPO is enabled and selected as the system clock. If another sys-
tem clock source is required or IPO disabling is required, the Stop Mode Recovery code
must reconfigure the oscillator control block such that the correct system clock source is
enabled and selected.
PS024315-1011
PRELIMINARY
Stop Mode Recovery