Z8F0113HJ005EG Datasheet, PDF (72/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
57
• Execution of an Return from Interrupt (IRET) instruction
• Writing a 1 to the IRQE bit in the Interrupt Control Register
Interrupts are globally disabled by any of the following actions:
• Execution of a Disable Interrupt (DI) instruction
• eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller
• Writing a 0 to the IRQE bit in the Interrupt Control Register
• Reset
• Execution of a Trap instruction
• Illegal Instruction Trap
• Primary Oscillator Fail Trap
• Watchdog Timer Oscillator Fail Trap
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all
interrupts are enabled with identical interrupt priority (for example, all as Level 2 inter-
rupts), the interrupt priority is assigned from highest to lowest as specified in Table 35 on
page 55. Level 3 interrupts are always assigned higher priority than Level 2 interrupts
which, in turn, always are assigned higher priority than Level 1 interrupts. Within each
interrupt priority level (Level 1, Level 2 or Level 3), priority is assigned as specified in
Table 35. Reset, Watchdog Timer interrupt (if enabled), Primary Oscillator Fail Trap,
Watchdog Timer Oscillator Fail Trap, and Illegal Instruction Trap always have highest
(Level 3) priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period (sin-
gle pulse). When the interrupt request is acknowledged by the eZ8 CPU, the correspond-
ing bit in the Interrupt Request register is cleared until the next interrupt occurs. Writing a
0 to the corresponding bit in the Interrupt Request register likewise clears the interrupt
request.
Caution: Zilog recommends not using a coding style that clears bits in the Interrupt Request reg-
isters. All incoming interrupts received between execution of the first LDX command
and the final LDX command are lost. See Example 1, which follows.
PS024315-1011
PRELIMINARY
Operation