Z8F0113HJ005EG Datasheet, PDF (80/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
65
IRQ2 Enable High and Low Bit Registers
Table 45 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit reg-
isters (Table 46 and Table 47) form a priority encoded enabling for interrupts in the Inter-
rupt Request 2 register. Priority is generated by setting bits in each register.
Table 45. IRQ2 Enable and Priority Encoding
IRQ2ENH[x] IRQ2ENL[x] Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
Note: where x indicates the register bits from 0–7.
Table 46. IRQ2 Enable High Bit Register (IRQ2ENH)
Bit
7
Field
RESET
0
R/W
R/W
Address
6
5
Reserved
0
0
R/W
R/W
4
3
C3ENH
0
0
R/W
R/W
FC7H
2
C2ENH
0
R/W
1
C1ENH
0
R/W
0
C0ENH
0
R/W
Bit
[7:4]
[3]
C3ENH
[2]
C2ENH
[1]
C1ENH
[0]
C0ENH
Description
Reserved
These bits are reserved and must be programmed to 0000.
Port C3 Interrupt Request Enable High Bit
Port C2 Interrupt Request Enable High Bit
Port C1 Interrupt Request Enable High Bit
Port C0 Interrupt Request Enable High Bit
PS024315-1011
PRELIMINARY
Interrupt Control Register Definitions