Z8F0113HJ005EG Datasheet, PDF (101/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
86
Timer 0–1 PWM High and Low Byte Registers
The Timer 0–1 PWM High and Low Byte (TxPWMH and TxPWML) registers (Table 55
and Table 56) control pulse-width modulator (PWM) operations. These registers also store
the capture values for the CAPTURE and CAPTURE/COMPARE modes.
Table 55. Timer 0–1 PWM High Byte Register (TxPWMH)
Bit
7
6
5
4
3
2
1
0
Field
PWMH
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F04H, F0CH
Table 56. Timer 0–1 PWM Low Byte Register (TxPWML)
Bit
7
6
5
4
3
2
1
0
Field
PWML
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F05H, F0DH
Bit
[7:0]
PWMH,
PWML
Description
Pulse-Width Modulator High and Low Bytes
These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the current
16-bit timer count. When a match occurs, the PWM output changes state. The PWM output
value is set by the TPOL bit in the Timer Control Register (TxCTL1) 
register.

These TxPWMH and TxPWML registers also store the 16-bit captured timer value when oper-
ating in CAPTURE or CAPTURE/COMPARE modes.
Timer 0–1 Control Registers
The Timer Control registers are 8-bit read/write registers that control the operation of their
associated counter/timers.
Timer 0–1 Control Register 0
The Timer Control Register 0 (TxCTL0) and Timer Control Register 1 (TxCTL1) deter-
mine the timer operating mode. It also includes a programmable PWM deadband delay,
PS024315-1011
PRELIMINARY
Timer Control Register Definitions