Z8F0113HJ005EG Datasheet, PDF (10/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
x
List of Figures
Figure 1. Z8 Encore! XP F0823 Series Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Z8F08x3, Z8F04x3, F02x3 and Z8F01x3 in 8-Pin SOIC, QFN/MLF-S, 
or PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Z8F08x3, Z8F04x3, F02x3 and Z8F01x3 in 20-Pin SOIC, SSOP 
or PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Z8F08x3, Z8F04x3, F02x3 and Z8F01x3 in 28-Pin SOIC, SSOP 
or PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 7. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 8. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 9. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 10. UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 11. UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . . . . . . 99
Figure 12. UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . . . . . . 99
Figure 13. UART Asynchronous MULTIPROCESSOR Mode Data Format . . . . . . 103
Figure 14. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity) 105
Figure 15. UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . . . . . 107
Figure 16. Infrared Data Communication System Block Diagram . . . . . . . . . . . . . . 117
Figure 17. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 18. IrDA Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 19. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . 122
Figure 20. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 21. Flash Controller Operation Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 22. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 23. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, 
# 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 24. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, 
# 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 25. OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 26. Opcode Map Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 27. First Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 28. Second Opcode Map after 1FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 29. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
PS024315-1011
PRELIMINARY
List of Figures