Z8F0113HJ005EG Datasheet, PDF (83/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
68
Interrupt Control Register
The Interrupt Control (IRQCTL) Register (Table 50) contains the master enable bit for all
interrupts.
Table 50. Interrupt Control Register (IRQCTL)
Bit
7
6
5
4
3
2
1
0
Field
IRQE
Reserved
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R
R
R
R
R
R
R
Address
FCFH
Bit
[7]
IRQE
[6:0]
Description
Interrupt Request Enable
This bit is set to 1 by executing an Enable Interrupts (EI) or Interrupt Return (IRET) instruction,
or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI instruction, eZ8
CPU acknowledgement of an interrupt request, reset or by a direct register write of a 0 to this
bit.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
Reserved
These bits are reserved and must be programmed to 0000000 when read.
PS024315-1011
PRELIMINARY
Interrupt Control Register Definitions