Z8F0113HJ005EG Datasheet, PDF (122/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
107
occurred, this byte cannot contain valid data and must be ignored. The BRKD bit indicates
if the overrun was caused by a break condition on the line. After reading the status byte
indicating an overrun error, the Receive Data Register must be read again to clear the error
bits is the UART Status 0 Register. Updates to the Receive Data Register occur only when
the next data word is received.
UART Data and Error Handling Procedure
Figure 15 displays the recommended procedure for use in UART receiver interrupt service
routines.
Receiver
Ready
Receiver
Interrupt
Read Status
No
Errors?
Yes
Read Data which
clears RDA bit and
resets error bits
Read Data
Discard Data
Figure 15. UART Receiver Interrupt Service Routine Flow
PS024315-1011
PRELIMINARY
Operation