Z8F0113HJ005EG Datasheet, PDF (74/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
59
Caution: To avoid retriggerings of the Watchdog Timer interrupt after exiting the associated inter-
rupt service routine, Zilog recommends that the service routine continues to read from
the RSTSTAT register until the WDT bit is cleared as shown in the following example.
CLEARWDT:
LDX r0, RSTSTAT ; read reset status register to clear wdt bit
BTJNZ 5, r0, CLEARWDT ; loop until bit is cleared
Interrupt Control Register Definitions
For all interrupts other than the Watchdog Timer interrupt, the Primary Oscillator Fail
Trap, and the Watchdog Timer Oscillator Fail Trap, the interrupt control registers enable
individual interrupts, set interrupt priorities, and indicate interrupt requests.
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) register (Table 36) stores the interrupt requests for both
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the Interrupt
Request 0 register to determine if any interrupt requests are pending.
Table 36. Interrupt Request 0 Register (IRQ0)
Bit
7
6
Field
Reserved T1I
RESET
0
0
R/W
R/W
R/W
Address
5
4
3
T0I
U0RXI U0TXI
0
0
0
R/W
R/W
R/W
FC0H
2
1
Reserved
0
R/W
0
ADCI
0
R/W
Bit
Description
[7]
Reserved
This bit is reserved and must be programmed to 0.
[6]
Timer 1 Interrupt Request
T1I
0 = No interrupt request is pending for Timer 1.
1 = An interrupt request from Timer 1 is awaiting service.
[5]
Timer 0 Interrupt Request
T0I
0 = No interrupt request is pending for Timer 0.
1 = An interrupt request from Timer 0 is awaiting service.
PS024315-1011
PRELIMINARY
Interrupt Control Register Definitions