Z8F0113HJ005EG Datasheet, PDF (108/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
93
WDT Reset in NORMAL Operation
If configured to generate a Reset when a time-out occurs, the Watchdog Timer forces the
device into the System Reset state. The WDT status bit in the Watchdog Timer Control
Register is set to 1. For more information about System Reset, see the Reset and Stop
Mode Recovery chapter on page 21.
WDT Reset in STOP Mode
If configured to generate a Reset when a time-out occurs and the device is in STOP Mode,
the Watchdog Timer initiates a Stop Mode Recovery. Both the WDT status bit and the
STOP bit in the Watchdog Timer Control Register are set to 1 following WDT time-out in
STOP Mode. For more information, see the Reset and Stop Mode Recovery chapter on
page 21.
Watchdog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watchdog Timer Control Register (WDTCTL) address
unlocks the three Watchdog Timer Reload Byte Registers (WDTU, WDTH, and WDTL)
to allow changes to the time-out period. These write operations to the WDTCTL Register
address produce no effect on the bits in the WDTCTL Register. The locking mechanism
prevents spurious writes to the Reload registers. The following sequence is required to
unlock the Watchdog Timer Reload Byte Registers (WDTU, WDTH, and WDTL) for
write access.
1. Write 55H to the Watchdog Timer Control Register (WDTCTL).
2. Write AAH to the Watchdog Timer Control Register (WDTCTL).
3. Write the Watchdog Timer Reload Upper Byte register (WDTU).
4. Write the Watchdog Timer Reload High Byte register (WDTH).
5. Write the Watchdog Timer Reload Low Byte register (WDTL).
All three Watchdog Timer Reload registers must be written in the order just listed. There
must be no other register writes between each of these operations. If a register write
occurs, the lock state machine resets and no further writes can occur unless the sequence is
restarted. The value in the Watchdog Timer Reload registers is loaded into the counter
when the Watchdog Timer is first enabled and every time a WDT instruction is executed.
Watchdog Timer Control Register Definitions
This section defines the features of the following Watchdog Timer Control registers.
Watchdog Timer Control Register (WDTCTL): see page 94
Watchdog Timer Reload Upper Byte Register (WDTU): see page 95
PS024315-1011
PRELIMINARY
Watchdog Timer Control Register