Z8F0113HJ005EG Datasheet, PDF (182/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
167
Table 102. OCD Control Register (OCDCTL)
Bit
7
6
5
4
Field
DBGMODE BRKEN DBGACK
RESET
0
0
0
0
R/W
R/W
R/W
R/W
R
3
2
Reserved
0
0
R
R
1
0
RST
0
0
R
R/W
Bit
Description
[7]
DEBUG Mode
DBGMODE The device enters DEBUG Mode when this bit is 1. When in DEBUG Mode, the eZ8 CPU
stops fetching new instructions. Clearing this bit causes the eZ8 CPU to restart. This bit is
automatically set when a BRK instruction is decoded and breakpoints are enabled. If the
Flash Read Protect Option Bit is enabled, this bit can only be cleared by resetting the
device. It cannot be written to 0.
0 = F0823 Series device is operating in NORMAL Mode.
1 = F0823 Series device is in DEBUG Mode.
[6]
BRKEN
Breakpoint Enable
This bit controls the behavior of the BRK instruction (opcode 00H). By default, breakpoints
are disabled and the BRK instruction behaves similar to an NOP instruction. If this bit is 1,
when a BRK instruction is decoded, the DBGMODE bit of the OCDCTL register is automati-
cally set to 1.
0 = Breakpoints are disabled.
1 = Breakpoints are enabled.
[5]
DBGACK
Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a
Debug Acknowledge character (FFH) to the host when a Breakpoint occurs.
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
[4:1]
Reserved
These bits are reserved and must be 00000 when read.
[0]
RST
Reset
Setting this bit to 1 resets the Z8F04xA family device. The device goes through a normal
Power-On Reset sequence with the exception that the OCD is not reset. This bit is automat-
ically cleared to 0 at the end of reset.
0 = No effect.
1 = Reset the Flash Read Protect Option Bit device.
PS024315-1011
PRELIMINARY
On-Chip Debugger Control Register