Z8F0113HJ005EG Datasheet, PDF (71/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
56
Architecture
Figure 8 displays the interrupt controller block diagram.
Port Interrupts
Internal Interrupts
High
Priority
Medium
Priority
Vector
Priority
Mux
IRQ Request
Low
Priority
Figure 8. Interrupt Controller Block Diagram
Operation
This section describes the operational aspects of the following functions.
Master Interrupt Enable: see page 56
Interrupt Vectors and Priority: see page 57
Interrupt Assertion: see page 57
Software Interrupt Assertion: see page 58
Watchdog Timer Interrupt Assertion: see page 58
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control Register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
• Execution of an Enable Interrupt (EI) instruction
PS024315-1011
PRELIMINARY
Architecture