Z8F0113HJ005EG Datasheet, PDF (173/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
158
RS-232 TX
RS-232 RX
RS-232
Transceiver
VDD
Open-Drain
Buffer
10 k
DBG Pin
Figure 24. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, # 2 of 2
DEBUG Mode
The operating characteristics of the devices in DEBUG Mode are:
• The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to ex-
ecute specific instructions
• The system clock operates unless in STOP Mode
• All enabled on-chip peripherals operate unless in STOP Mode
• Automatically exits HALT Mode
• Constantly refreshes the Watchdog Timer, if enabled.
Entering DEBUG Mode
The device enters DEBUG Mode following the operations below:
• The device enters DEBUG Mode after the eZ8 CPU executes a BRK (breakpoint) in-
struction
• If the DBG pin is held Low during the most recent clock cycle of System Reset, the part
enters DEBUG Mode upon exiting System Reset
Note: Holding the DBG pin Low for an additional 5000 (minimum) clock cycles after reset
(making sure to account for any specified frequency error if using an internal oscillator)
prevents a false interpretation of an autobaud sequence (see the OCD Autobaud Detector/
Generator section on page 159).
PS024315-1011
PRELIMINARY
Operation