Z8F0113HJ005EG Datasheet, PDF (107/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
92
Watchdog Timer Refresh
When first enabled, the WDT is loaded with the value in the Watchdog Timer Reload reg-
isters. The Watchdog Timer counts down to 000000H unless a WDT instruction is executed
by the eZ8 CPU. Execution of the WDT instruction causes the down counter to be reloaded
with the WDT reload value stored in the Watchdog Timer Reload registers. Counting
resumes following the reload operation.
When Z8 Encore! XP F0823 Series devices are operating in DEBUG Mode (using the
OCD), the Watchdog Timer is continuously refreshed to prevent any Watchdog Timer
time-outs.
Watchdog Timer Time-Out Response
The Watchdog Timer times out when the counter reaches 000000H. A time-out of the
Watchdog Timer generates either an interrupt or a system reset. The WDT_RES Flash
Option Bit determines the time-out response of the Watchdog Timer. For information
about programming of the WDT_RES Flash Option Bit, see the Flash Option Bits chapter
on page 146.
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the Watchdog Timer issues
an interrupt request to the interrupt controller and sets the WDT status bit in the Watchdog
Timer Control Register. If interrupts are enabled, the eZ8 CPU responds to the interrupt
request by fetching the Watchdog Timer interrupt vector and executing code from the vec-
tor address. After time-out and interrupt generation, the Watchdog Timer counter rolls
over to its maximum value of FFFFFH and continues counting. The Watchdog Timer
counter is not automatically returned to its Reload Value.
The Reset Status Register (see the Reset Status Register section on page 28) must be read
before clearing the WDT interrupt. This read clears the WDT time-out Flag and prevents
further WDT interrupts for immediately occurring.
WDT Interrupt in STOP Mode
If configured to generate an interrupt when a time-out occurs and F0823 Series are in
STOP Mode, the Watchdog Timer automatically initiates a Stop Mode Recovery and gen-
erates an interrupt request. Both the WDT status bit and the STOP bit in the Watchdog
Timer Control Register are set to 1 following a WDT time-out in STOP Mode. For more
information about Stop Mode Recovery, see the Reset and Stop Mode Recovery chapter
on page 21.
If interrupts are enabled, following completion of the Stop Mode Recovery the eZ8 CPU
responds to the interrupt request by fetching the Watchdog Timer interrupt vector and exe-
cuting code from the vector address.
PS024315-1011
PRELIMINARY
Operation